Package substrate and semiconductor package including the same

ABSTRACT

A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.

CROSS-RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.13/599,838, filed Aug. 30, 2012, which claims priority under 35 USC §119to Korean Patent Application No. 2011-93788, filed on Sep. 19, 2011 inthe Korean Intellectual Property Office (KIPO), the contents of each ofwhich are herein incorporated by reference in their entirety.

BACKGROUND

1. Field

Example embodiments relate to a package substrate and/or a semiconductorpackage including the same. More particularly, example embodimentsrelate to a package substrate on which a semiconductor chip is mountedvia conductive bumps, and/or a semiconductor package including thepackage substrate.

2. Description of the Related Art

Generally, a plurality of semiconductor fabrication processes may beperformed on a semiconductor substrate to form a plurality ofsemiconductor chips. In order to mount the semiconductor chips on aprinted circuit board (PCB), a packaging process may be performed on thesemiconductor chips to form semiconductor packages.

The semiconductor package may include a package substrate, asemiconductor chip arranged over the package substrate, and signal bumpsinterposed between the semiconductor chip and the package substrate. Thesignal bumps may electrically connect bonding pads of the semiconductorchip with signal pads of the package substrate. A passivation layerhaving openings configured to expose the bonding pads may be formed on alower surface of the semiconductor chip. Thus, the passivation layer mayhave a lower surface, lower than that of the bonding pads.

In order to reinforce a bonding strength between the package substrateand the semiconductor chip, dummy bumps may be interposed between thepackage substrate and the semiconductor chip. The dummy bumps may beinterposed between the passivation layer of the semiconductor chip anddummy pads of the package substrate. The dummy bumps may have athickness substantially the same as that of the signal bumps.

Because the lower surface of the passivation layer on the semiconductorchip may protrude downwardly from the lower surface of the bonding padand the thickness of the dummy bump formed on the passivation layer maybe substantially the same as that of the signal bump formed on thebonding pad, the signal bump may not make contact with the signal pad,although the dummy bump may make contact with the dummy pad. As aresult, although the dummy bump may reinforce the bonding strengthbetween the semiconductor chip and the package substrate, thesemiconductor package may frequently have electrical disconnections.

SUMMARY

At least one example embodiment provides a package substrate having areinforced bonding strength and improved electrical connectionreliability.

At least one example embodiment also provides a package substrateincluding the above-mentioned package substrate.

According to one example embodiment, there is provided a packagesubstrate. The package substrate may include an insulating substrate, adummy pad, a signal pad and a plug. The insulating substrate may have anupper surface on which a semiconductor chip may be mounted via a signalbump and a dummy bump having substantially the same thickness. The dummypad may be formed on the upper surface of the insulating substrate. Thedummy pad may be electrically connected with the dummy bump. The signalpad may be formed on the upper surface of the insulating substrate. Thesignal pad may be electrically connected with the signal bump. Further,the signal pad may have an upper surface protruded from an upper surfaceof the dummy pad. The plug may be vertically formed in the insulatingsubstrate. The plug may have an upper end exposed through the uppersurface of the insulating substrate and connected with the signal padand the dummy pad, and a lower end exposed through a lower surface ofthe insulating substrate.

In an example embodiment, the signal pad may be arranged on a centralportion of the upper surface of the insulating substrate. The dummy padmay be arranged on an edge portion of the upper surface of theinsulating substrate.

In an example embodiment, the signal pad may be arranged on an edgeportion of the upper surface of the insulating substrate. The dummy padmay be arranged on a central portion of the upper surface of theinsulating substrate.

In an example embodiment, the package substrate may further include anupper insulating layer pattern formed on the upper surface of theinsulating substrate to expose the signal pad and the dummy pad, and alower insulating layer pattern formed on the lower surface of theinsulating substrate to exposed the lower end of the plug.

In an example embodiment, the package substrate may further include anupper conductive layer comprising the dummy pad and the signal pad.

In an example embodiment, the package substrate may further include afirst portion of the upper conductive layer including the protrusion.The thickness of the protrusion may ensure electrical connectivitybetween the signal bump and the signal pad.

According to one example embodiment, there is provided a semiconductorpackage. The semiconductor package may include a package substrate, asemiconductor chip, a signal bump and a dummy bump. The packagesubstrate may include a dummy pad and a signal pad protruded from anupper surface of the dummy pad. The semiconductor chip may be arrangedover the package substrate. The semiconductor chip may include a bondingpad, and a passivation layer having a lower surface protruded from thatof the bonding pad. The signal bump may be interposed between thebonding pad of the semiconductor chip and the signal pad of the packagesubstrate. The dummy bump may be interposed between the passivationlayer of the semiconductor chip and the dummy pad of the packagesubstrate. The signal bump and the dummy bump may have substantially thesame thickness.

In an example embodiment, the signal pad and the signal bump may bearranged on a central portion of an upper surface of the insulatingsubstrate. The dummy pad the dummy bump may be arranged on an edgeportion of an upper surface of the insulating substrate.

In an example embodiment, the signal pad and the signal bump may bearranged on an edge portion of the upper surface of the insulatingsubstrate. The dummy pad and the dummy bump may be arranged on a centralportion of the upper surface of the insulating substrate.

In an example embodiment, the semiconductor package may further includea molding member formed on the upper surface of the package substrate tocover the semiconductor chip.

In an example embodiment, the semiconductor package may further includeexternal terminals mounted on a lower surface of the package substrate.The external terminals may be electrically connected to the signal pad.

In an embodiment, the protrusion may have a thickness that ensureselectrical connectivity between the signal bump and the signal pad.

According to one example embodiment, there is provided a semiconductorpackage. The semiconductor package may include a package substrate, asemiconductor chip, a signal bump and a dummy bump. The packagesubstrate may include a dummy pad and a signal pad. The semiconductorchip may be arranged over the package substrate. The semiconductor chipmay include a bonding pad, and a passivation layer having a lowersurface protruded from that of the bonding pad. The dummy bump may beinterposed between the passivation layer of the semiconductor chip andthe dummy pad of the package substrate. The signal bump may beinterposed between the bonding pad of the semiconductor chip and thesignal pad of the package substrate. The signal bump may have athickness greater than that of the dummy bump to make contact with thesignal pad.

In an example embodiment, a thickness difference between the signal bumpand the dummy bump may correspond to a thickness of a portion of thepassivation layer protruded from the bonding pad.

In an example embodiment, the signal pad and the signal bump may bearranged on a central portion of an upper surface of the insulatingsubstrate. The dummy pad the dummy bump may be arranged on an edgeportion of an upper surface of the insulating substrate.

In an example embodiment, the signal pad and the signal bump may bearranged on an edge portion of the upper surface of the insulatingsubstrate. The dummy pad and the dummy bump may be arranged on a centralportion of the upper surface of the insulating substrate.

In an example embodiment, the semiconductor package may further includea molding member formed on the upper surface of the package substrate tocover the semiconductor chip.

In an example embodiment, the semiconductor package may further includeexternal terminals mounted on a lower surface of the package substrate.The external terminals may be electrically connected to the signal pad.

In an example embodiment, the thickness of the signal bump may besufficient to ensure electrical connectivity between the signal bump andthe signal pad.

According to example embodiments, the signal pad may be upwardlyprotruded from the dummy pad, so that the signal bump may accuratelymake contact with the protruded upper surface of the signal pad.Alternatively, the thickness of the signal bump may be thicker than thatof the dummy bump, so that an accurate contact between the signal bumpand the signal pad may be ensured. Therefore, the semiconductor packagemay have a strong bonding strength and improved electrical connectionreliability.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. FIGS. 1 to 9 represent non-limiting, example embodiments asdescribed herein.

FIG. 1 is a cross-sectional view illustrating a package substrate inaccordance with an example embodiment;

FIGS. 2 to 4 are cross-sectional views illustrating a method ofmanufacturing the package substrate in FIG. 1;

FIG. 5 is a cross-sectional view illustrating a semiconductor packageincluding the package substrate in FIG. 1;

FIG. 6 is an enlarged cross-sectional view of a portion VI of in FIG. 5;

FIG. 7 is a cross-sectional view illustrating a package substrate inaccordance with an example embodiment;

FIG. 8 is a cross-sectional view illustrating a semiconductor packageincluding the package substrate in FIG. 7; and

FIG. 9 is a cross-sectional view illustrating a semiconductor package inaccordance with an example embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exampleembodiments are shown. It should be understood, however, that there isno intent to limit example embodiments to the particular formsdisclosed, but to the contrary, example embodiments are to cover allmodifications, equivalents, and alternatives falling within the scope ofexample embodiments. In the drawings, the sizes and relative sizes oflayers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of thepresent invention. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, example embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, example embodiments will be explained in detail withreference to the accompanying drawings.

Package Substrate

FIG. 1 is a cross-sectional view illustrating a package substrate inaccordance with an example embodiment.

Referring to FIG. 1, a package substrate 100 of this example embodimentmay include an insulating substrate 110, an upper signal pad 120, adummy pad 124, a plug 130 and a lower signal pad 140.

In this example embodiment, the insulating substrate 110 may include aninsulating material. A semiconductor chip (not shown) may be mounted onan upper surface of the insulating substrate 110 via a signal bump (notshown) and a dummy bump (not shown). The semiconductor chip may includea bonding pad (not shown) and a passivation layer (not shown). Thus, thepackage substrate 100 may be used for packaging the semiconductor chipthat may include the bonding pad may be arranged on a central portion ofthe semiconductor chip. Therefore, the passivation layer may have alower surface, lower than that of the bonding pad. Further, thethickness of the signal bump may be substantially the same thickness asthat of the dummy bump. External terminals (not shown) may be mounted ona lower surface of the insulating substrate 110.

The upper signal pad 120 may be arranged on a central portion of theupper surface of the insulating substrate 110. In this exampleembodiment, the upper signal pad 120 may have a protrusion 122. Theprotrusion 122 may be formed on an upper surface of the upper signal pad120. The signal bump may make contact with the protrusion 122 of theupper signal pad 120.

The dummy pad 124 may be arranged on an edge portion of the uppersurface of the insulating substrate 110. In the example embodiment, thedummy pad 124 may have an upper surface substantially coplanar with thatof the upper signal pad 120. Thus, the upper surface of the dummy pad124 may be lower than the upper surface of the protrusion 122. The dummybump may make contact with the dummy pad 124. The dummy pad 124 may beelectrically connected with the upper signal pad 120.

In the example embodiment, the dummy bump may be formed on a lowersurface of the passivation layer. The signal bump may be formed on alower surface of the bonding pad, lower than the lower surface of thepassivation layer. Therefore, a lower surface of the signal bump, whichmay have the thickness substantially the same as that of the dummy bump,may be positioned higher than a lower surface of the dummy bump. As aresult, the lower surface of the signal bump may not make contact withthe upper signal pad 120.

In contrast, according to the example embodiment, because the uppersignal pad 120 may have the protrusion 122, the lower surface of thesignal bump may accurately make contact with the protrusion 122. Thatis, the protrusion 122 may serve to compensate for a difference betweena gap between the passivation layer and the dummy pad 124, and a gapbetween the bonding pad and the upper signal pad 120. Thus, theprotrusion 122 may have a thickness substantially the same as the gapdifference. Particularly, the thickness of the protrusion 122 may besubstantially the same as a thickness of a portion of the passivationlayer protruding from the bonding pad.

A plug 130 may be formed in the insulating substrate 110. The plug 130may have an upper end making contact with the upper signal pad 120, andthe plug 130 may have a lower end exposed through the lower surface ofthe insulating substrate 110. The external terminals may be mounted onthe lower end of the plug 130.

The lower signal pad 140 may be arranged on the lower surface of theinsulating substrate 110. The lower signal pad 140 may be electricallyconnected with the lower end of the plug 130.

An upper insulating layer pattern 150 may be formed on the upper surfaceof the insulating substrate 110. The upper insulating layer pattern 150may have openings configured to expose the upper signal pad 120 and thedummy pad 124.

A lower insulating layer pattern 152 may be formed on the lower surfaceof the insulating substrate 110. The lower insulating layer pattern 152may have openings configured to expose the lower signal pad 140.

According to this example embodiment, the upper signal pad 120 may havethe protrusion 122 higher than the dummy pad 124, so that the signalbump having the thickness substantially the same as that of the dummybump may accurately make contact with the protrusion 122.

FIGS. 2 to 4 are cross-sectional views illustrating a method ofmanufacturing the package substrate in FIG. 1.

Referring to FIG. 2, a plug 130 may be vertically oriented in theinsulating substrate 110. An upper conductive layer 126 may be formed onthe upper surface of the insulating substrate 110. A lower conductivelayer 146 may be formed on the lower surface of the insulating substrate110. The upper conductive layer 126 and the lower conductive layer 146may be connected with each other via the plug 130. In this exampleembodiment, the upper conductive layer 126 and the lower conductivelayer 146 may include a metal layer such as a copper layer.

Referring to FIG. 3, a mask 160 may be arranged over a central portion126 c of the upper conductive layer 126. The upper conductive layer 126may be half-etched using the mask 160 as an etch mask to form an upperconductive layer pattern 128. In this example embodiment, because thecentral portion 126 c of the upper conductive layer 126 may be coveredwith the mask 160, the central portion 126 c of the upper conductivelayer 126 may not be removed by the half-etching process. In contrast,an edge portion 126 e of the upper conductive layer 126 may be removedby the half-etching process, so that an etched edge portion 126 e of theupper conductive layer 126 may have a thickness of about 0.5 times athickness of the central portion 126 c of the upper conductive layer126. Thus, the upper conductive layer pattern 128 may have the centralprotrusion 122. After completing the half-etching process, the mask 160may then be removed.

In contrast, all portions of the lower conductive layer 146 may behalf-etched to form a lower conductive layer pattern 148. The lowerconductive layer pattern 148 may have a thickness of about 0.5 timesthat of the lower conductive layer 146.

Referring to FIG. 4, the upper conductive layer pattern 128 may bepatterned to form the upper signal pad 120 and the dummy pad 124. Inthis example embodiment, the upper signal pad 120 may have theprotrusion 122 higher than the upper surface of the dummy pad 124. Theupper signal pad 120 may be connected to the plug 130.

The lower conductive layer pattern 148 may be patterned to form thelower signal pad 140. The lower signal pad 140 may be connected to theplug 130. Therefore, the upper signal pad 120 and the lower signal pad140 may be connected with each other via the plug 130.

The upper insulating layer pattern 150 may be formed on the uppersurface of the insulating substrate 110. In this example embodiment, theupper insulating layer pattern 150 may have the openings configured toexpose the upper signal pad 120 and the dummy pad 124. The lowerinsulating layer pattern 152 may be formed on the lower surface of theinsulating substrate 110 to complete the package substrate 100 inFIG. 1. In this example embodiment, the lower insulating layer pattern152 may have the openings configured to expose the lower signal pad 140.

FIG. 5 is a cross-sectional view illustrating a semiconductor packageincluding the package substrate in FIG. 1, and FIG. 6 is an enlargedcross-sectional view of a portion VI of in FIG. 5.

Referring to FIGS. 5 and 6, a semiconductor package 200 of this exampleembodiment may include a package substrate 100, a semiconductor chip210, a signal bump 220, a dummy bump 230, a molding member 240 andexternal terminals 250. The package substrate 110 may have an edgeportion 100 e and a central portion 100 c.

In this example embodiment, the package substrate 100 may includeelements substantially the same as those of the package substrate 100 inFIG. 1. Thus, the same reference numerals may refer to the same elementsand any further illustrations with respect to the same element may beomitted herein for brevity.

The semiconductor chip 210 may be arranged over the package substrate100. The semiconductor chip 210 may have a bonding pad 212. In thisexample embodiment, the bonding pad 212 may be arranged on a centralportion of a lower surface of the semiconductor chip 210. A passivationlayer 214 may be formed on the lower surface of the semiconductor chip210. The passivation layer 214 may have openings configured to exposethe bonding pad 212. The passivation layer 214 may have a lower surface,lower than that of the bonding pad 212. Thus, a distance between thelower surface of the bonding pad 212 and the signal pad 120 may belonger than a distance between the lower surface of the passivationlayer 214 and the dummy pad 124.

The signal bump 220 may be interposed between the semiconductor chip 210and the package substrate 100. In this example embodiment, the signalbump 220 may be interposed between the bonding pad 212 of thesemiconductor chip 210 and the protrusion 122 of the upper signal pad120 of the package substrate 100. Electrical signals may be transmittedthrough the signal bump 220. Thus, the bonding pad 212 and the uppersignal pad 120 may be electrically connected with each other via thesignal bump 220.

In this example embodiment, the signal bump 220 may have a thicknesssubstantially the same as that of the dummy bump 230. As mentionedabove, because the distance between the lower surface of the bonding pad212 and the signal pad 120 may be longer than the distance between thelower surface of the passivation layer 214 and the dummy pad 124, thesignal bump 220 may not make contact with the upper signal pad 120.However, according to this example embodiment, the signal bump 220 maymake contact with the protrusion 122, functioning to compensate for thedistance difference. Therefore, an electrical connection between thesignal bump 220 and the upper signal pad 120 may be ensured by theprotrusion 122.

The dummy bump 230 may be interposed between the semiconductor chip 210and the package substrate 100. In this example embodiment, the dummybump 230 may be interposed between the passivation layer 214 of thesemiconductor chip 210 and the dummy pad 124 of the package substrate100. Thus, the electrical signals may not be transmitted through thedummy bump 230. The dummy bump 230 may reinforce a bonding strengthbetween the semiconductor chip 210 and the package substrate 100.

The molding member 240 may be disposed on the upper surface of thepackage substrate 100 to cover the semiconductor chip 210. In thisexample embodiment, the molding member 240 may include an epoxy moldingcompound (EMC).

The external terminals 250 may be mounted on the lower signal pad 140 ofthe package substrate 100. In this example embodiment, the externalterminals 250 may include solder balls.

According to this example embodiment, the signal bump 220, having athickness substantially the same as that of the dummy bump 230, may makecontact with the protrusion 122 of the signal pad 120. Thus, theelectrical connection between the semiconductor chip 210 and the packagesubstrate 110 may be ensured by the protrusion 122. As a result, thesemiconductor package 200 may have improved electrical connectionreliability.

FIG. 7 is a cross-sectional view illustrating a package substrate 110 ain accordance with example an embodiment.

A package substrate 100 a of this example embodiment may includeelements substantially the same as those of the package substrate 100 inFIG. 1 except for positions of a signal pad 120 a and a dummy pad 124 a.Thus, the same reference numerals may refer to the same elements and anyfurther illustrations with respect to the same element may be omittedherein for brevity.

Referring to FIG. 7, the package substrate 100 a of this exampleembodiment may include a signal pad 120 a and a dummy pad 124 a. Thesignal pad 120 a may be arranged on the edge portion 110 e of the uppersurface of the insulating substrate 110. In contrast, the dummy pad 124a may be arranged on the central portion 110 c of the upper surface ofthe insulating substrate 110. That is, the package substrate 100 a maybe used for packaging a semiconductor chip having bonding pads that maybe arranged on an edge portion of the semiconductor chip.

A method of manufacturing the package substrate 100 a may includeprocesses substantially the same as the method of manufacturing thepackage substrate 100 illustrated with reference to FIGS. 2 to 4 exceptfor a process for arranging the mask 160 over the edge portion of theinsulating substrate 100. Thus, any further illustrations with respectto the method of manufacturing the package substrate 100 a may beomitted herein for brevity.

FIG. 8 is a cross-sectional view illustrating a semiconductor package200 a including the package substrate 110 a in FIG. 7.

A semiconductor package 200 a of this example embodiment may includeelements substantially the same as those of the semiconductor package200 in FIG. 5 except for a semiconductor chip 210 a and a packagesubstrate 100 a. Thus, the same reference numerals may refer to the sameelements and any further illustrations with respect to the same elementmay be omitted herein for brevity.

Referring to FIG. 8, the semiconductor package 200 a of this exampleembodiment may include a bonding pad 212 a. The bonding pad 212 a may bearranged on an edge portion of the lower surface of the semiconductorchip 210 a. Thus, a signal bump 220 a may be interposed between edgeportions of a package substrate 100 a and the semiconductor chip 210 a.In contrast, a dummy bump 230 a may be interposed between centralportions of the package substrate 100 a and the semiconductor chip 210a.

FIG. 9 is a cross-sectional view illustrating a semiconductor package inaccordance with an example embodiment.

Referring to FIG. 9, a semiconductor package 200 b of this exampleembodiment may include a package substrate 100 b, a semiconductor chip210, a signal bump 220 b, a dummy bump 230 b, a molding member 240 andexternal terminals 250.

In this example embodiment, the semiconductor chip 210, the moldingmember 240 and the external terminals 250 may be substantially the sameas the semiconductor chip 210, the molding member 240 and the externalterminals 250 in FIG. 6. Thus, any further illustrations with respect tothe semiconductor chip 210, the molding member 240 and the externalterminals 250 may be omitted herein for brevity.

In this example embodiment, the package substrate 100 b may not have aprotrusion. That is, the protrusion may not be formed on the uppersurface of the upper signal pad 120. Thus, the upper surface of theupper signal pad 120 may be positioned substantially coplanar with theupper surface of the dummy pad 124.

The signal bump 220 b may be interposed between the semiconductor chip210 and the package substrate 100 b. In this example embodiment, thesignal bump 220 b may be interposed between the bonding pad 212 of thesemiconductor chip 210 and the upper signal pad 120 of the packagesubstrate 100 b. Electrical signals may be transmitted through thesignal bump 220 b.

In this example embodiment, the signal bump 220 b may have a thicknessgreater than that of the dummy bump 230 b. As mentioned above, becausethe distance between the lower surface of the bonding pad 212 and thesignal pad 120 may be longer than the distance between the lower surfaceof the passivation layer 214 and the dummy pad 124, the signal bump 220b may not make contact with the upper signal pad 120. However, accordingto this example embodiment, the signal bump 220 b having the thicknessgreater than that of the dummy bump 230 b may make contact with theupper signal pad 120.

The dummy bump 230 b may be interposed between the semiconductor chip210 and the package substrate 100 b. In this example embodiment, thedummy bump 230 b may be interposed between the passivation layer 214 ofthe semiconductor chip 210 and the dummy pad 124 of the packagesubstrate 100 b. The dummy bump 230 b may reinforce a bonding strengthbetween the semiconductor chip 210 and the package substrate 100 b.

According to this example embodiment, the signal bump 220 b having thethickness greater than that of the dummy bump 230 b may make contactwith the signal pad 120. Thus, the electrical connection between thesemiconductor chip 210 and the package substrate 100 b may be ensured bythe thick signal bump 220 b. As a result, the semiconductor package 200b may have improved electrical connection reliability.

According to this example embodiment, the signal pad 120 may be upwardlyprotruded from the dummy pad 124, so that the signal bump 220 b mayaccurately make contact with the protrusion 122 on the upper surface ofthe signal pad 120. Alternatively, the thickness of the signal bump 220b may be thicker than that of the dummy bump 230 b, so that an accuratecontact between the signal bump 220 b and the signal pad 120 may beensured. Therefore, the semiconductor package 200 b may have a strongbonding strength and improved electrical connection reliability.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Example embodiments having thus beendescribed, it will be obvious that the same may be varied in many ways.Such variations are not to be regarded as a departure from the intendedspirit and scope of example embodiments, and all such modifications aswould be obvious to one skilled in the art are intended to be includedwithin the scope of the following claims.

What is claimed is:
 1. A package substrate comprising: an insulatingsubstrate having an upper surface on which a semiconductor chip isarranged via a signal bump and a dummy bump, the signal bump and thedummy bump having substantially the same thickness; a dummy pad havingan upper surface, the dummy pad on the upper surface of the insulatingsubstrate and connected to the dummy bump; a signal pad formed on theupper surface of the insulating substrate and connected to the signalbump, the signal pad having a protrusion that has an upper surfacehigher than the upper surface of the dummy pad; and a plug having anupper end and a lower end, the upper end exposed through the uppersurface of the insulating substrate and electrically connected with thesignal pad and the dummy pad, and the lower end exposed through a lowersurface of the insulating substrate.